When a multi level inverter outputs

When a multi level inverter outputs an intermediate voltage level, not 0or (m-1)⋅Vdc, only
one clamping diode in each phase leg conducts current at any instant in time where as half of the
active switches are conducting at all times. Which diode is conducting current is determined by
which intermediate dc voltage level is connected to the output phase conductor and by which
direction the current is flowing, positive or negative. For instance, when a phase leg of the series
inverter in Figure 31.28 is connected to level V4, then diode D2conducts for current flowing from
the inverter to the electrical system, and diode D3conducts for current flowing into the inverter
fromthe electrical system.
This example illustrates that for current flowing out of an inverter, only the clamping
diodes in the top half of a phase leg will conduct,and for current flowing into an inverter, only
the clamping diodes in the bottom half of the phase leg will conduct.In all like lihood the current
wave forms will be odd symmetric. These facts alone enable the average current rating for the
clamping diodes to be at most one half that of the active devices. The clamping diodes should all
have a pulse or short time current rating equal to the amplitude of the maximum compensation
current that the inverter is expected to conduct. Generally, this is equal to 2times the value
calculated inequation (31.31) or (31.35) for the series and parallel inverters, respectively.

When a multi level inverter outputs an intermediate voltage level, not 0or (m-1)⋅Vdc, only 
one clamping diode in each phase leg conducts current at any instant in time where as half of the 
active switches are conducting at all times. Which diode is conducting current is determined by
which intermediate dc voltage level is connected to the output phase conductor and by which 
direction the current is flowing, positive or negative. For instance, when a phase leg of the series 
inverter in Figure 31.28 is connected to level V4, then diode D2conducts for current flowing from
the inverter to the electrical system, and diode D3conducts for current flowing into the inverter 
fromthe electrical system. 
This example illustrates that for current flowing out of an inverter, only the clamping 
diodes in the top half of a phase leg will conduct,and for current flowing into an inverter, only
the clamping diodes in the bottom half of the phase leg will conduct.In all like lihood the current
wave forms will be odd symmetric. These facts alone enable the average current rating for the 
clamping diodes to be at most one half that of the active devices. The clamping diodes should all 
have a pulse or short time current rating equal to the amplitude of the maximum compensation 
current that the inverter is expected to conduct. Generally, this is equal to 2times the value 
calculated inequation (31.31) or (31.35) for the series and parallel inverters, respectively.

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When a multi level inverter outputs an intermediate voltage level, not 0or (m-1)⋅Vdc, only one clamping diode in each phase leg conducts current at any instant in time where as half of the active switches are conducting at all times. Which diode is conducting current is determined bywhich intermediate dc voltage level is connected to the output phase conductor and by which direction the current is flowing, positive or negative. For instance, when a phase leg of the series inverter in Figure 31.28 is connected to level V4, then diode D2conducts for current flowing fromthe inverter to the electrical system, and diode D3conducts for current flowing into the inverter fromthe electrical system. This example illustrates that for current flowing out of an inverter, only the clamping diodes in the top half of a phase leg will conduct,and for current flowing into an inverter, onlythe clamping diodes in the bottom half of the phase leg will conduct.In all like lihood the currentwave forms will be odd symmetric. These facts alone enable the average current rating for the clamping diodes to be at most one half that of the active devices. The clamping diodes should all have a pulse or short time current rating equal to the amplitude of the maximum compensation current that the inverter is expected to conduct. Generally, this is equal to 2times the value calculated inequation (31.31) or (31.35) for the series and parallel inverters, respectively.

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Ketika inverter multi level output tingkat menengah tegangan, tidak 0or (m-1) ⋅Vdc, hanya
satu menjepit dioda di setiap kaki fase melakukan saat ini setiap instan dalam waktu di mana setengah dari
switch aktif melakukan setiap saat. Yang dioda sedang melakukan saat ini ditentukan oleh
tingkat mana dc tegangan menengah yang terhubung ke konduktor fase output dan dimana
arah arus mengalir, positif atau negatif. Misalnya, ketika kaki fase seri
inverter pada Gambar 31,28 terhubung ke tingkat V4, maka dioda D2conducts untuk arus yang mengalir dari
inverter ke sistem listrik, dan D3conducts dioda untuk arus yang mengalir ke inverter
dari dana sistem listrik.
Contoh ini menggambarkan bahwa untuk saat ini mengalir keluar dari inverter, hanya menjepit
dioda di bagian atas kaki fase akan melakukan, dan arus yang mengalir ke inverter, hanya
dioda penjepit di bagian bawah kaki fase akan conduct.In semua suka lihood saat
bentuk gelombang akan simetris aneh. Fakta-fakta ini sendiri memungkinkan nilai sekarang rata-rata untuk
dioda menjepit menjadi paling banyak satu setengah dari perangkat aktif. Dioda penjepit semua harus
memiliki pulsa atau waktu singkat nilai sekarang sama dengan amplitudo maksimum kompensasi
yang saat inverter diharapkan untuk melakukan. Umumnya, ini sama dengan 2times nilai
dihitung inequation (31,31) atau (31,35) untuk seri dan paralel inverter, masing-masing.

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